Fix fuzzer.c nits and replace CLZ fallback
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+10
-6
@@ -51,12 +51,16 @@ MEM_STATIC unsigned ZSTD_countTrailingZeros32(U32 val)
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MEM_STATIC unsigned ZSTD_countLeadingZeros32_fallback(U32 val) {
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MEM_STATIC unsigned ZSTD_countLeadingZeros32_fallback(U32 val) {
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assert(val != 0);
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assert(val != 0);
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{
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{
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unsigned result = 0;
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static const U32 DeBruijnClz[32] = {0, 9, 1, 10, 13, 21, 2, 29,
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while ((val & 0x80000000) == 0) {
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11, 14, 16, 18, 22, 25, 3, 30,
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result++;
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8, 12, 20, 28, 15, 17, 24, 7,
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val <<= 1;
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19, 27, 23, 6, 26, 5, 4, 31};
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}
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val |= val >> 1;
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return result;
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val |= val >> 2;
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val |= val >> 4;
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val |= val >> 8;
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val |= val >> 16;
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return DeBruijnClz[(val * 0x07C4ACDDU) >> 27] ^ 31;
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}
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}
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}
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}
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+18
-6
@@ -3377,22 +3377,26 @@ static int basicUnitTests(U32 const seed, double compressibility)
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DISPLAYLEVEL(3, "test%3i : testing bitwise instrinsics PR#3045: ", testNb++);
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DISPLAYLEVEL(3, "test%3i : testing bitwise instrinsics PR#3045: ", testNb++);
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{
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{
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U32 seed_32 = seed == 0 ? seed + 1 : seed; // these intrinsics are undefined on 0
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U32 seed_copy = seed; // need non-const seed to avoid compiler warning for FUZ_rand(&seed)
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U64 seed_64 = (U64)seed * 0x87654321; // decent 64-bit distribution
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U32 rand32 = FUZ_rand(&seed_copy);
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U64 rand64 = ((U64)FUZ_rand(&seed_copy) << 32) | FUZ_rand(&seed_copy);
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U32 lowbit_only_32 = 1;
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U32 lowbit_only_32 = 1;
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U64 lowbit_only_64 = 1;
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U64 lowbit_only_64 = 1;
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U32 highbit_only_32 = (U32)1 << 31;
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U32 highbit_only_32 = (U32)1 << 31;
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U64 highbit_only_64 = (U64)1 << 63;
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U64 highbit_only_64 = (U64)1 << 63;
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U32 i;
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if (rand32 == 0) rand32 = 1; // CLZ and CTZ are undefined on 0
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if (rand64 == 0) rand64 = 1; // CLZ and CTZ are undefined on 0
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/* Test ZSTD_countTrailingZeros32 */
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/* Test ZSTD_countTrailingZeros32 */
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CHECK_EQ(ZSTD_countTrailingZeros32(lowbit_only_32), 0u);
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CHECK_EQ(ZSTD_countTrailingZeros32(lowbit_only_32), 0u);
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CHECK_EQ(ZSTD_countTrailingZeros32(highbit_only_32), 31u);
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CHECK_EQ(ZSTD_countTrailingZeros32(highbit_only_32), 31u);
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CHECK_EQ(ZSTD_countTrailingZeros32(seed_32), ZSTD_countTrailingZeros32_fallback(seed_32));
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CHECK_EQ(ZSTD_countTrailingZeros32(rand32), ZSTD_countTrailingZeros32_fallback(rand32));
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/* Test ZSTD_countLeadingZeros32 */
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/* Test ZSTD_countLeadingZeros32 */
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CHECK_EQ(ZSTD_countLeadingZeros32(lowbit_only_32), 31u);
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CHECK_EQ(ZSTD_countLeadingZeros32(lowbit_only_32), 31u);
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CHECK_EQ(ZSTD_countLeadingZeros32(highbit_only_32), 0u);
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CHECK_EQ(ZSTD_countLeadingZeros32(highbit_only_32), 0u);
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CHECK_EQ(ZSTD_countLeadingZeros32(seed_32), ZSTD_countLeadingZeros32_fallback(seed_32));
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CHECK_EQ(ZSTD_countLeadingZeros32(rand32), ZSTD_countLeadingZeros32_fallback(rand32));
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/* Test ZSTD_countTrailingZeros64 */
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/* Test ZSTD_countTrailingZeros64 */
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CHECK_EQ(ZSTD_countTrailingZeros64(lowbit_only_64), 0u);
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CHECK_EQ(ZSTD_countTrailingZeros64(lowbit_only_64), 0u);
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@@ -3426,8 +3430,16 @@ static int basicUnitTests(U32 const seed, double compressibility)
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}
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}
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/* Test MEM_ intrinsics */
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/* Test MEM_ intrinsics */
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CHECK_EQ(MEM_swap32(seed_32), MEM_swap32_fallback(seed_32));
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CHECK_EQ(MEM_swap32(rand32), MEM_swap32_fallback(rand32));
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CHECK_EQ(MEM_swap64(seed_64), MEM_swap64_fallback(seed_64));
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CHECK_EQ(MEM_swap64(rand64), MEM_swap64_fallback(rand64));
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/* Test fallbacks vs intrinsics on a range of small integers */
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for (i=1; i <= 1000; i++) {
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CHECK_EQ(MEM_swap32(i), MEM_swap32_fallback(i));
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CHECK_EQ(MEM_swap64((U64)i), MEM_swap64_fallback((U64)i));
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CHECK_EQ(ZSTD_countTrailingZeros32(i), ZSTD_countTrailingZeros32_fallback(i));
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CHECK_EQ(ZSTD_countLeadingZeros32(i), ZSTD_countLeadingZeros32_fallback(i));
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}
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}
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}
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DISPLAYLEVEL(3, "OK \n");
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DISPLAYLEVEL(3, "OK \n");
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